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From VLSI fundamentals to advanced tape-out — structured learning, open-source projects, real automation flows, and expert career services. Built by practitioners from Qualcomm and Cadence.

17 Learning modules Open-source projects ISAR automation flow Expert career services
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Product

ISAR Workflow

A Python-based EDA automation flow for physical design and signoff — collecting PnR and timing metrics, generating interactive HTML dashboards, automating ECO runs, and enabling run comparison. Deployed at Bosch and Infineon through Cadence.

Metric collection
Automatically collects PPA metrics across PnR and signoff runs — timing, area, power, congestion.
HTML dashboards
Auto-generated interactive HTML reports with run comparison, trend analysis, and drill-down views.
ECO automation
Automated ECO generation and application for setup and hold closure — reduces manual iteration time.
Run comparison
Side-by-side comparison of multiple PnR trials with delta analysis for PPA and timing.
Learn the flow Discuss your project
isar_flow / dashboard.html
Run comparison — Trial 03 vs Trial 04
01Setup WNS-12ps → +8ps ✓
02Hold WNS-5ps → 0ps ✓
03Area (mm²)4.82 → 4.71 ↓
04Leakage (mW)12.4 → 11.1 ↓
05Congestion87% → 82% ↓
06DRC violationsClean ✓
Trial 04 recommended for signoff handoff
Services

Expert support at every stage

From personal career coaching to corporate training and ASIC consulting — choose the support that fits your need.

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Individual
Career counselling
A focused 1:1 session for ASIC engineers — career roadmap, role transitions, and industry insights from 9+ years at Qualcomm and Cadence.
Career roadmap & role transition
Resume & LinkedIn review
ASIC interview preparation
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Corporate
Corporate training
Custom training programs for engineering teams — full ASIC flow, EDA automation, low power design, or topic-specific workshops.
Custom curriculum design
Online or on-site delivery
Workshops & webinars
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Consulting
Project consulting
Hands-on technical consulting for ASIC and EDA automation projects — flow review, PPA strategy, Python scripting, and freelance project support.
EDA flow review & optimisation
Freelance EDA development
Automation strategy
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Articles & updates

Latest from SiliconSetu

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Place & route
Clock tree synthesis strategies for low-power designs with high fan-in paths in Innovus
A deep-dive into CTS methodologies for complex low-power SoC designs — H-tree vs mesh, latency balancing, and cross-corner hold strategies from a real 4nm tape-out.
10 min read·5 comments·Login to read
Static timing analysis
Hold violations in Tempus: root causes and systematic ECO closure
12 min·8
 EDA automation
Building the ISAR flow: Python metric collection with HTML dashboards
15 min·14
 RTL design
Clock domain crossing: metastability, synchronisers and CDC analysis
9 min·6
 VLSI fundamentals
Understanding CMOS inverter: operation, sizing, and power
8 min·11
Learning modules

Structured ASIC education

All 17 modules
Backend · Module 05
Place & route
Physical implementation — floorplanning, power planning, placement, CTS, routing, congestion, and PPA optimisation from real 3nm–11nm tape-outs.
FloorplanningCTSRoutingPPA
8 sub-modules · 14 articlesOpen
Signoff · Module 08
Static timing analysis
STA closure in industry-standard tools — setup/hold analysis, MMMC, ECO generation, CPPR, OCV, and practical debug from real tape-outs.
MMMCECOCPPROCV
6 sub-modules · 11 articlesOpen
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Automation · Module 16
EDA automation flow
End-to-end ISAR flow — metric collection, HTML dashboards, run comparison, ECO automation, and CI integration for design teams.
PythonDashboardsECOCI
4 sub-modules · 7 articlesOpen
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PV
Pankaj Verma
Founder · Principal AE at Cadence Design Systems · Munich
9+ years physical design IIT Bombay M.Tech · 9.44 CGPA 10+ tape-outs · 3nm–11nm Qualcomm · Cadence
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