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SiliconSetu
Full ASIC flow · Free to read

Master the complete
ASIC design flow

Bridging Silicon. Empowering Innovation.

Bridging Silicon. Empowering Innovation. — Structured learning modules covering every stage of chip design from specification to tape-out, powered by real industry experience from Qualcomm and Cadence.

Semiconductor learning · 17 modules
AI-powered EDA workflows
Connecting talent to industry
Always free to read
Learning modules

The complete ASIC design flow

17 modules across 5 phases — in design order. Click any module to see what's covered, sub-topics, and articles.

EDA Essentials
Frontend
Backend
Signoff
Automation
Design flow order
EDA Essentials3
VLSI fundamentals
CMOSLogic gates
4 topics · 7 articles
Semiconductor basics
MOSFETProcess nodes
3 topics · 5 articles
EDA tools overview
Flow overviewOpen-source
3 topics · 5 articles
Frontend4
Specification
Design specPower budget
5 topics · 8 articles
RTL design
HDLCDC/RDCLint
6 topics · 10 articles
Functional verification
UVMFormalCoverage
5 topics · 9 articles
Design for test (DFT)
ScanATPGBIST
4 topics · 6 articles
Backend3
Logic synthesis
RTL-to-netlistSDCMMMC
5 topics · 7 articles
Place & route
FloorplanCTSPPA
8 topics · 14 articles
Low power design
Power intentMulti-voltage
4 topics · 6 articles
Signoff5
Static timing analysis
STAECOMMMC
6 topics · 11 articles
Physical verification
DRCLVS
4 topics · 7 articles
Power integrity
IR dropEM analysis
4 topics · 6 articles
Logical equivalence
LECFormal equiv.
3 topics · 4 articles
Tape-out & delivery
GDSIIChecklist
3 topics · 5 articles
Automation2
Scripting for EDA
PythonTCLShell
6 topics · 10 articles
EDA automation flow
Metric collectionDashboards
4 topics · 7 articles
Open-source projects

Learn by building real designs

Step-by-step guided projects using open-source EDA tools. Each project walks you through a complete design flow with code, scripts, and explanations.

In progress
OpenROAD full ASIC flow
Complete RTL-to-GDSII walkthrough using OpenROAD and the SkyWater 130nm PDK. Covers synthesis, placement, routing, and DRC signoff.
OpenROADSkyWater 130nmYosysKLayout
Coming soon
Python PnR report parser
Build a Python tool that parses timing and area reports, collects metrics, and generates an interactive HTML dashboard — inspired by the ISAR flow.
PythonHTML dashboardReport parsing
Coming soon
RISC-V core — RTL to GDS
Take an open-source RISC-V core from RTL through synthesis, placement, routing, and full signoff. A complete real-world design exercise.
RISC-VSystemVerilogFull flow
View all projects
Latest articles

From the knowledge base

Practical deep-dives from real tape-out experience. Every article has a community comment section.

Place & route
Clock tree synthesis strategies for low-power designs with high fan-in paths
10 min 5 comments
Static timing analysis
Hold violations: root causes, debug strategies and systematic ECO closure
12 min 8 comments
EDA automation flow
PnR metric collection with Python: building an HTML reporting dashboard
15 min 14 comments
RTL design
Clock domain crossing: metastability, synchronisers and lint-based CDC analysis
9 min 6 comments
Physical verification
Automating DRC waiver management with Python scripting
11 min 7 comments
VLSI fundamentals
Understanding CMOS inverter: operation, sizing, and power dissipation
8 min 11 comments
View all articles
Services

Work directly with an expert

From 1-on-1 career sessions to corporate training programs and freelance ASIC consulting — choose the support that fits your need.

Most popular
Career counselling
A focused 1:1 session to navigate your ASIC career — whether starting out, moving roles, or planning your next move in the industry.
Career roadmap & role transition strategy
Industry insights from real experience
60-minute video call
Book a session
Resume & profile review
Detailed review of your resume and LinkedIn from a hiring-manager perspective in the semiconductor industry.
Written feedback within 3 days
ASIC-specific terminology & framing
30-min follow-up call included
Request a review
ASIC interview prep
Mock interview and coaching for physical design and signoff roles — technical questions and what hiring teams actually want.
Full mock interview (45 min)
STA, P&R & signoff question bank
Detailed debrief & improvement plan
Book a session
Corporate training
Structured multi-session training programs for engineering teams covering the full ASIC flow, automation, or specific technical domains.
Custom curriculum for your team's needs
Online or on-site delivery
Hands-on labs & practical exercises
Post-training Q&A and support
Get in touch
Workshops & webinars
Focused half-day or full-day workshops on specific ASIC topics — timing closure, EDA automation, low power design, and more.
Topic-focused intensive sessions
Live Q&A and discussion
Slides & materials included
Enquire now
Team capability review
An assessment of your team's current ASIC flow maturity — identifying gaps, recommending improvements, and building a learning roadmap.
Gap analysis & skill mapping
Learning roadmap document
Follow-up recommendations
Get in touch
Project consultation
Technical consultation on your ASIC design or EDA automation project — flow review, bottleneck analysis, and recommendations from an experienced practitioner.
EDA flow review & optimisation
PPA & closure strategy advice
Written report with action items
Start a conversation
Freelance EDA projects
Hands-on involvement in your ASIC or EDA automation work — scripting, flow development, report automation, or signoff support.
Python / TCL automation development
EDA flow setup & debugging
Flexible engagement model
Discuss your project
Automation strategy
Help your team plan and implement an EDA automation strategy — from scripting foundations to a full metric-driven flow like ISAR.
Current flow assessment
Automation roadmap design
Implementation guidance & review
Get in touch
PV
Pankaj Verma
Principal Application Engineer · Cadence Design Systems · Munich
9+ years physical design IIT Bombay M.Tech 10+ tape-outs · 3nm–11nm Qualcomm · Cadence
View full profile