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SiliconSetu Founder
PV

Pankaj Verma

Principal Application Engineer · Digital & Signoff Group · Cadence Design Systems GmbH · Munich, Germany

9+ years in physical design — from research at IIT Bombay to leading PD teams at Qualcomm across 10+ tape-outs at 3nm–11nm, to supporting Cadence customers at Bosch, Infineon, Apple Semiconductor and Renesas Europe. Built QSAR at Qualcomm and the ISAR flow at Cadence — both Python-based automation frameworks for PnR and signoff. Founded SiliconSetu to make this knowledge openly available to the next generation of chip design engineers.

LinkedIn pankajverma.pd@gmail.com Book a session Munich, Germany
9+Years in physical design
10+Tape-outs led
3nmSmallest node experience
9.44IIT Bombay CGPA
QSARBuilt at Qualcomm
ISARBuilt at Cadence
Technical expertise

Core skills & tools

PD implementation
Cadence InnovusSynopsys ICC2Fusion CompilerFloorplanningCTSRoutingPPA optimisation
Signoff
PrimeTimeTempusCalibre DRC/LVSVoltusDorado TweakerECO closure
Automation & scripting
PythonTCLPerlShellLSF / SlurmHTML reports
HDL & design
VerilogSystemVerilogVHDLSystemCCC++
Experience

Career timeline

Jul 2024
Present
Cadence
Principal Application Engineer
Digital & Signoff Group · Munich, Germany
Technical support and business growth for major European customers — Robert Bosch Semiconductor, Infineon, Renesas Europe, and Apple Semiconductor. Responsible for all Cadence tool evaluation and flow deployment for digital implementation and signoff.
Built the new Python-based ISAR flow with enhanced HTML-based PNR tracking and metric collection for Bosch
Developed Voltus InsightAI flow to auto-fix static and dynamic IR violations through the PnR flow at Infineon
Full Innovus and Tempus technical support for Apple Semiconductor and Renesas Europe
Jul 2016
Jul 2024
Qualcomm
Staff Engineer — Physical Design
Video / EVA Core Team Lead · Bangalore, India · 8 years
Led PD teams of 6–10 engineers for 10+ tape-outs across Automobile, AR/XR, and Compute segments at 3nm to 11nm. Built and deployed QSAR — a Python automation framework used org-wide across the Video/EVA team.
10+ tape-outs from 3nm to 11nm — end-to-end PD implementation and full signoff closure
Consistently achieved 1–2% SU growth and ~10% leakage benefits per project cycle
Built QSAR: Python GUI automating PnR trials, signoff runs, ECO generation and single-window reporting
Contributed ~$1M saving by identifying a missed SoC bump in the package team handoff
Implemented Cerebrus-based ML trials for CTS and placement optimisation — first adoption in multimedia PD team
Jul 2013
Jun 2016
IIT Bombay
Research Assistant
Device Characterization Lab · M.Tech Research
Managed 9 measurement systems with 150+ users. Mentored 200+ engineers nationwide as part of the Indian Nano-electronics User Program. Published at IEEE ISVLSI 2016 and IEEE IRPS 2014.
IEEE ISVLSI 2016: "On-chip Delay Measurement Circuit for SRAM Reliability Characterization" · Pittsburgh, USA
Indian Patent: On-chip Delay Measurement Circuit · Publication No. 40/2018
Key tape-outs

Selected physical design projects

4nm · Automobile
Video / EVA core · Auto SoC
Team lead · ~45M gates · 12 HMs · Team of 12
New architecture with 18% higher frequency targets. End-to-end tape-out in 30 weeks. Cerebrus-based PPA model development with Cadence AEs.
InnovusCerebrus ML30 weeks
4nm · AR/XR
Video core · AR/XR platform
Team lead · ~26M gates · 10LM · Team of 9
8.5% area saving vs HLDR, 4% higher SU. Cerebrus CTS trials reduced latency by 18%. H-tree implementation for robust cross-corner hold benefits.
InnovusPrimeTimeCerebrus CTS
3nm · First silicon
Video core · MSM 3nm
Team lead · ~14M gates · Team of 7
First 3nm tape-out. Implemented 2.5K SoC pipeline feedthroughs through hardmacros. New flow PoR adopted for future 3nm projects.
InnovusPrimeTimeNew node PoR
5nm · Automobile
Video core · 5nm Auto
Team lead · ~14M gates · Team of 7
5% area saving, 30% less leakage than target. Hierarchical carve-out saved 50 hrs PnR runtime with 47% leakage benefit — became PoR for future projects.
InnovusHier carve-out47% leakage win
4nm · First 4nm
Video core · MSM 4nm
Team lead · ~17M gates · Innovus + FC
Late PDK release caused 1L+ setup violations 3 weeks before BTO. Aggressive ECO plan closed timing on a large fan-in cone design within the timeline.
InnovusFusion CompilerEmergency ECO
Python · Org tool
QSAR · Qualcomm automation flow
Creator & maintainer · Org-wide deployment
Python-based GUI automating PnR trials, signoff runs, timing ECO generation, and single-window metric reporting across the entire Video/EVA organisation.
PythonGUIAuto-ECOMulti-tool
Education

Academic background

M.Tech — Microelectronics & VLSI
Indian Institute of Technology (IIT) Bombay
CGPA 9.44 / 10 · 2013 – 2016
B.Tech — Electronics & Communication Engineering
National Institute of Technology (NIT) Bhopal
CGPA 8.23 / 10 · 2009 – 2013
Publications & patents

Research output

P. Verma — "Qualcomm Signoff Automation and Reporting Flow (QSAR)" · QBuzz 2020 Video Paper
Internal publication · Qualcomm · 2020
P. Verma, H. Patel, R. Halba, M. S. Baghini — "On-chip Delay Measurement Circuit" · Indian Patent, Publication No. 40/2018
Intellectual Property India · October 2018
P. Verma, H. Patel, R. Halba, M. S. Baghini — "On-chip Delay Measurement Circuit for Reliability Characterization of SRAM" · IEEE ISVLSI 2016, Pittsburgh, USA
IEEE Computer Society Annual Symposium on VLSI · 2016
T. Naphade, P. Verma, N. Goel, S. Mahapatra — "DC/AC BTI Variability of SRAM Circuits Simulated Using a Physics-Based Compact Model" · IEEE IRPS 2014, Hawaii, USA
International Reliability Physics Symposium · IEEE · 2014
Founded by Pankaj Verma

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